Semiconductor memory devices such as DRAMs and SRAMs are making significant gains in data output speed and bandwidth and their integration density is increasing. The timing gap between the output data hold time (tOH) and the clock to valid output delay time (tSAC) is an important parameter in synchronous memories because of the importance of the burst access mode of operation. This is because the clock cycle time (tCC) depends on the timing gap. The clock cycle time is the sum of tOH, tSAC, and the timing gap between tOH and tSAC. The tOH and tSAC are determined by the rising and falling transition times, respectively. Accordingly, if the timing gap increases, the clock cycle time will increase and the bandwidth will decrease. Increases in the timing gap between tOH and tSAC may be caused by variations in power supply voltage and temperature, or by impedance mismatch between data output pins.
To inhibit increases in the timing gap between tOH and tSAC due to power supply voltage variations, a data output buffer may be supplied with a stable internal power supply voltage and an external power supply. For example, a conventional data output buffer may include a pull-up MOS transistor having its current path electrically coupled in series between an external power supply voltage and a data output pad and a pull-down transistor having its current path electrically coupled in series between the data output pad and a reference power supply voltage (such as ground voltage). In order to gain speed, the gate electrode of the pull-up MOS transistor may be supplied with a boosted voltage which is determined by the internal power supply voltage.
However, if a higher external power supply voltage is applied to semiconductor memory device with the above-described data output buffer arrangement, the source-drain voltage of the pull-up MOS transistor may increase and this increase may cause additional skew between the output high voltage (VOH) and the output low voltage (VOL) since the current driving capability of the pull-up MOS transistor is increased. When this occurs, the rising transition time becomes shorter while the falling transition time remains unchanged. Thus, the bandwidth of the memory device may be reduced because tOH becomes shorter and tSAC becomes longer.